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_______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. max3945 1.0625gbps to 11.3gbps, sfp+ dual-path limiting amplifier 19-5144; rev 0; 2/10 general description the max3945 is a +3.3v, multirate, low-power limiting amplifier optimized for fibre channel and ethernet trans - mission systems at data rates up to 11.3gbps. the high- sensitivity limiting amplifier limits the signal generated by a transimpedance amplifier into a cml-level differential output signal. all differential inputs and outputs (i/o) are optimally back terminated for 50 i transmission line pcb design. the max3945s dual-path limiting amplifier has programmable filtering to optimize sensitivity for differ - ent data rates and to suppress relaxation oscillations that could occur in some optical systems. the max3945 incorporates two loss-of-signal (los) circuits and a pro - grammable time mask for the los output. a 3-wire digital interface reduces the pin count and enables control of los threshold, los polarity, los mode, cml output level, input offset correction, receive (rx) polarity, rx input filter, and rx deemphasis without the need for external components. the max3945 is packaged in a 3mm x 3mm, 16-pin tqfn package. applications 1x/2x/4x/8x sff/sfp/sfp+ msa fibre-channel optical transceiver 10gbase-sr/lr sfp+ optical transceiver 10g pon onu ordering information features s 130mw power dissipation enables < 1w sfp+ modules s enables single-module design compliance with 1000base-sx/lx and 10gbase-sr/lr specifications s -25.3dbm optical sensitivity at 1.25gbps using a 10.32gbps rosa s selectable 1ghz/2.1ghz/2.5ghz/3ghz input filters at rate_sel = 0 setting s supports sff-8431 sfp+ msa and sff-8472 digital diagnostic s total power dissipation of 130mw at 3.3v power supply with rssi monitor-based los s total power dissipation of 154mw at 3.3v power supply with rx input-based los s 4mv p-p input sensitivity at 11.3gbps s 4ps p-p dj at 11.3gbps with rate_sel = 1 s 4ps p-p dj at 8.5gbps with rate_sel = 1 s 5ps p-p dj at 4.25gbps with rate_sel = 0, bw1 = 1, bw0 = 1 s 9.0ps p-p dj at 1.25gbps with rate_sel = 0, bw1 = 0, bw0 = 0 s 26ps rise and fall time with rate_sel = 1 s 52ps rise and fall time with rate_sel = 0 s cml output with level adjustment and squelch mode s programmable cml output deemphasis s cml output polarity select s los polarity select s programmable masking time for the los output s los assert/deassert level adjustment s choice of rx input-based los or rssi monitor- based los s 3-wire digital interface compatible with maxims sfp+ family of products + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. typical application circuit appears at end of data sheet. evaluation kit available part temp range pin-package MAX3945ETE+ -40 n c to +85 n c 16 tqfn-ep*
2 ______________________________________________________________________________________ max3945 1.0625gbps to 11.3gbps, sfp+ dual-path limiting amplifier stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc ....................................................................... -0.3v to +4.0v voltage range at sda, scl, csel, los, caz, rpmin ................................. -0.3v to (v cc + 0.3v) voltage range at rout+, rout- ........ (v cc - 2v) to (v cc + 0.3v) voltage range at rin+, rin- ........ (v cc - 1.7v) to (v cc + 0.3v) current range into los ...................................... -1ma to +5ma current range into sda ..................................... -1ma to +1ma current out of rout+, rout- .......................................... 40ma continuous power dissipation (t a = +70 n c) 16-pin tqfn (derate 14.7mw/ n c above +70 n c) ......... 1.176w operating junction temperature range ......... -55 n c to +150 n c storage temperature range ............................ -65 n c to +160 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c electrical characteristics (v cc = 2.85v to 3.63v, cml receiver output is ac-coupled to differential 100 i load, c caz = 0.1 f f, t a = -40 n c to +85 n c. registers are set to default values, unless otherwise noted. typical values are at v cc = 3.3v, t a = +25 n c, unless otherwise noted.) absolute maximum ratings parameter symbol conditions min typ max units power supply power-supply current i cc includes the cml output current, v diff_rout = 400mv p-p , rxde_en = 0, los1_en = 1, los2_en = 0 46.6 62 ma includes the cml output current, v diff_rout = 400mv p-p , rxde_en = 0, los1_en = 0, los2_en = 1 39.4 52.5 power-supply voltage v cc 2.85 3.63 v power-supply noise f < 10mhz 100 mv p-p 10mhz < f < 20mhz 10 general input data rate 1.06 10.32 11.3 gbps input/output snr 14.1 ber 10e-12 power-on reset (por) por deassert threshold 2.55 2.75 v por assert threshold 2.3 2.45 v input specifications differential input resistance rin+/rin- r in_diff 75 100 125 i input sensitivity (note 1) v inmin rate_sel = 1, input transition time 25ps, 10.32gbps, prbs23-1 pattern 4 8 mv p-p rate_sel = 0, input transition time 260ps, 1.25gbps, k28.5 pattern 1 2 input overload v inmax 1.2 v p-p input return loss sdd11 dut is powered on, f p 5ghz 10 db dut is powered on, f p 16ghz 7 scc11 dut is powered on, 1ghz < f p 5ghz 13 db dut is powered on, 1ghz < f p 16ghz 5 rpmin input-current high i ih los1_en = 0 and los2_en = 1, v rpmin = 2v 50 na
_______________________________________________________________________________________ 3 max3945 1.0625gbps to 11.3gbps, sfp+ dual-path limiting amplifier electrical characteristics (continued) (v cc = 2.85v to 3.63v, cml receiver output is ac-coupled to differential 100 i load, c caz = 0.1 f f, t a = -40 n c to +85 n c. registers are set to default values, unless otherwise noted. typical values are at v cc = 3.3v, t a = +25 n c, unless otherwise noted.) parameter symbol conditions min typ max units external rpmin filter capacitor 100 pf output specifications differential output resistance rout+/rout- r outdiff 75 100 125 i output return loss sdd22 dut is powered on, f p 5ghz 13 db dut is powered on, f p 16ghz 7 scc22 dut is powered on, 1ghz < f p 5ghz 10 dut is powered on, 1ghz < f p 16ghz 6 differential output-voltage high 5mv p-p p v in p 1200mv p-p , rate_sel = 0, set_cml[7:0] = 169d (decimal) 595 800 1005 mv p-p 10mv p-p p v in p 1200mv , rate_sel = 1, set_cml[7:0] = 181d 595 800 1005 differential output-voltage medium 10mv p-p p v in p 1200mv p-p, rate_sel = 1, set_cml[7:0] = 91d 300 400 515 mv p-p set_cml dac range 60 255 decimal differential output signal when squelched (note 1) outputs ac-coupled, set_cml[7:0] = 181d, at 8.5gbps, sq_en = 1 6 15 mv p-p data output transition time (20% to 80%) (note 1) t r /t f 60mv p-p p v in p 400mv p-p at 10.32gbps, rate_sel = 1, v diff_rout = 400mv p-p , rxde_en = 0, input transition time 25ps, p attern 11110000 26 35 ps 10mv p-p p v in p 1200mv p-p at 1.25gbps, rate_sel = 0, v diff_rout = 800mv p-p , i nput transition time 260ps, p attern 11110000 52 90 transfer characteristics deterministic jitter (notes 1, 2) dj 10mv p-p p v in p 1200mv p-p at 8.5gbps, rate_sel = 1, v diff_rout = 400mv p-p , rxde_en = 0, input transition time 28ps 4 8 ps p-p 60 mv p-p p v in p 400mv p-p at 10.32gbps, rate_sel = 1, v diff_rout = 400mv p-p , rxde_en = 0, input transition time 28ps 4 9 60 mv p-p p v in p 400mv p-p at 11.3gbps, rate_sel = 1, v diff_rout = 400mv p-p , rxde_en = 0, input transition time 28ps 4 9 10 mv p-p p v in p 1200mv p-p at 1.25gbps, rate_sel = 0, bw1 = 0, bw0 = 0, v diff_rout = 800mv p-p , input transition time 260ps 9 30 10 mv p-p p v in p 1200mv p-p at 4.25gbps, rate_sel = 0, bw1 = 1, bw0 = 1, v diff_rout = 800mv p-p , input transition time 28ps 5 10
4 ______________________________________________________________________________________ max3945 1.0625gbps to 11.3gbps, sfp+ dual-path limiting amplifier electrical characteristics (continued) (v cc = 2.85v to 3.63v, cml receiver output is ac-coupled to differential 100 i load, c caz = 0.1 f f, t a = -40 n c to +85 n c. registers are set to default values, unless otherwise noted. typical values are at v cc = 3.3v, t a = +25 n c, unless otherwise noted.) parameter symbol conditions min typ max units random jitter (note 1) rj input = 60mv p-p at 10.32gbps , rate_sel = 1, rxde_en = 0, input transi - tion time 28ps, pattern 11110000, v diff_rout = 800mv p-p 0.28 0.51 ps rms low-frequency cutoff (simulated value) rate_sel = 0, c caz = 0.1 f f 2 khz rate_sel = 1, c caz = 0.1 f f 0.7 small-signal bandwidth (simulated value) f 3db rate_sel = 0, bw1 = 0, bw0 = 0 1.0 ghz rate_sel = 0, bw1 = 0, bw0 = 1 2.1 rate_sel = 0, bw1 = 1, bw0 = 0 2.5 rate_sel = 0, bw1 = 1, bw0 = 1 3.0 rate_sel = 1 9 rx input-based los specifications (los1_en = 1 and los2_en = 0) (note 1) los assert sensitivity range (note 3) 14 77 mv p-p set_los dac range 7 63 decimal los hysteresis 10log(v deassert /v assert ) 1.25 2.1 db los assert/deassert time (note 4) 2.3 20 80 f s low assert level set_los[5:0] = 7d (note 3) 8 11 14 mv p-p low deassert level 14 18 22 medium assert level set_los[5:0] = 32d (note 3) 39 49 58 mv p-p medium deassert level 65 82 95 high assert level set_los[5:0] = 63d (note 3) 77 96 112 mv p-p high deassert level 127 158 182 los output masking time range set_lostimer[6:0] = 0d for minimum and set_lostimer[6:0] = 127d for maximum 0 2920 f s los output masking dac resolution set_lostimer[6:0] = 1d to 127d 23 35 50 f s rssi monitor-based los specifications (los1_en = 0 and los2_en = 1) (note 1) los assert sensitivity range (note 5) 8.3 90 mv set_los dac range 4 63 decimal los hysteresis 10log(v deassert /v assert ) 1.25 2.1 db los assert/deassert time (note 4) 2.3 20 80 f s low assert level set_los[5:0] = 4d (note 5) 5.1 6.7 8.3 mv low deassert level 9.0 10.8 12.7 medium assert level set_los[5:0] = 32d (note 5) 45 50 55 mv medium deassert level 77 85 92 high assert level set_los[5:0] = 63d (note 5) 90 98 106 mv high deassert level 153 167 180 los output masking time range set_lostimer[6:0] = 0d for minimum and set_lostimer[6:0] = 127d for maximum 0 2920 f s los output masking dac resolution set_lostimer[6:0] = 1d to 127d 23 35 50 f s
_______________________________________________________________________________________ 5 max3945 1.0625gbps to 11.3gbps, sfp+ dual-path limiting amplifier electrical characteristics (continued) (v cc = 2.85v to 3.63v, cml receiver output is ac-coupled to differential 100 i load, c caz = 0.1 f f, t a = -40 n c to +85 n c. registers are set to default values, unless otherwise noted. typical values are at v cc = 3.3v, t a = +25 n c, unless otherwise noted.) parameter symbol conditions min typ max units output level voltage dac (set_cml) full-scale voltage v fs 100 i differential resistive load, rxde_en = 0 1192 mv p-p 100 i differential resistive load, rate_sel = 1, rxde_en = 1, rxde1 = 1, rxde0 = 1 (maximum deemphasis) 828 resolution 100 i differential resistive load, rxde_en = 0 4.5 mv p-p 100 i differential resistive load, rate_sel = 1, rxde_en = 1, rxde1 = 1, rxde0 = 1 (maximum deemphasis) 3.3 integral nonlinearity inl set_cml[7:0] > 60d q 0.9 lsb los threshold voltage dac (set_los) full-scale voltage v fs los1_en = 1, los2_en = 0 96 mv p-p los1_en = 0, los2_en = 1 98 mv resolution los1_en = 1, los2_en = 0 1.52 mv p-p los1_en = 0, los2_en = 1 1.56 mv integral nonlinearity inl set_los[5:0] > 3d q 0.7 lsb control i/o specifications los output high voltage v oh r los = 4.7k i to 10k i to v cc v cc - 0.5 v cc v los output low voltage v ol r los = 4.7k i to 10k i to v cc 0 0.4 v 3-wire digital i/o specifications (sda, csel, scl) input high voltage v ih 2.0 v cc v input low voltage v il 0.8 v input hysteresis v hyst 0.082 v input leakage current i il,ih v in = 0v or v cc , internal pullup or pulldown (75k i typ) 85 f a output high voltage v oh external pullup of 4.7k i to v cc v cc - 0.5 v cc v output low voltage v ol external pullup of 4.7k i to v cc 0 0.4 v 3-wire digital interface timing characteristics (see figure 5) scl clock frequency f scl 0 400 1000 khz scl pulse-width high t ch 500 ns scl pulse-width low t cl 500 ns sda setup time t ds 100 ns sda hold time t dh 100 ns scl rise to sda propagation time t d 5 ns csel pulse-width low t csw 500 ns
6 ______________________________________________________________________________________ max3945 1.0625gbps to 11.3gbps, sfp+ dual-path limiting amplifier electrical characteristics (continued) (v cc = 2.85v to 3.63v, cml receiver output is ac-coupled to differential 100 i load, c caz = 0.1 f f, t a = -40 n c to +85 n c. registers are set to default values, unless otherwise noted. typical values are at v cc = 3.3v, t a = +25 n c, unless otherwise noted.) note 1: guaranteed by design and characterization, t a = -40 n c to +95 n c. note 2: deterministic jitter is measured with a repeating k28.5 pattern [00111110101100000101] for 1.25gbps to 8.5gbps data. at 10.32gbps and 11.3gbps, a repeating k28.5 plus 59 0s and k28.5 plus 59 1s pattern is used. deterministic jitter is defined as the arithmetic sum of pulse-width distortion (pwd) and pattern-dependent jitter (pdj). note 3: los1_en = 1, data rates of 1.25gbps to 8.5gbps with k28.5 pattern, and 6.4ghz input filter. for data rates of 10.32gbps to 11.3gbps, the input filter is 12.5ghz and the pattern is prbs23-1. note 4: measurement includes an input ac-coupling capacitor of 100nf and c caz of 100nf. the signal at the rin or rpmin input is switched between two amplitudes: signal_on and signal_off. 1) receiver operates at sensitivity level plus 1db power penalty a) signal_off = 0 signal_on = (+8db) + 10log(min_assert_level) b) signal_on = (+1db) + 10log(max_deassert_level) signal_off = 0 2) receiver operates at overload signal_off = 0 signal_on = 1.2v p-p max_deassert_level and min_assert_level are measured for one set_los setting note 5: los1_en = 0, los2_en = 1, dc voltage applied to the rpmin input. parameter symbol conditions min typ max units csel leading time before the first scl edge t l 500 ns csel trailing time after the last scl edge t t 500 ns sda, scl external load c b total bus capacitance on one line with 4.7k i to v cc 20 pf
_______________________________________________________________________________________ 7 max3945 1.0625gbps to 11.3gbps, sfp+ dual-path limiting amplifier typical operating characteristics (v cc = 3.3v, t a = +25 n c, unless otherwise noted. registers are set to default values, unless otherwise noted, and the 3-wire interface is static during measurements.) receive output from optical system, 10.32gbps, optical input -10dbm, rxde1 = 1, rxde0 = 0 max3945 toc01 receive output from optical system, 10.32gbps, optical input -15dbm, rxde1 = 1, rxde0 = 0 max3945 toc02 receive output from optical system, 10.32gbps, optical input -20dbm, rxde1 = 1, rxde0 = 0 max3945 toc03 optical ber curves (nec nr3312) max3945 toc04 average power dbm (er~12db) ber -22 -23 -26 -25 -24 1.00e-11 1.00e-10 1.00e-09 1.00e-08 1.00e-07 1.00e-06 1.00e-05 1.00e-04 1.00e-03 1.00e-02 1.00e-01 1.00e-12 -27 -21 10.3gbps, prbs31, rate_sel = 1 4.5gbps, prbs9, rate_sel = 1 8.5gbps, prbs9, rate_sel = 1 4.5gbps, prbs9, rate_sel = 0, bw1 = 1, bw0 = 1 1.25gbps, prbs9, rate_sel = 0, bw1 = 1, bw0 = 1 1.25gbps, prbs9, rate_sel = 0, bw1 = 0, bw0 = 0 k28.5 pattern at 1.25gbps, set_cml[7:0] = 169d, rate_sel = 0, bw0 = 0, bw1 = 0 max3945 toc05 200ps/div 100mv/div k28.5 pattern at 4.25gbps, set_cml[7:0] = 169d, rate_sel = 0, bw0 = 1, bw1 = 1 max3945 toc06 50ps/div 100mv/div k28.5 pattern at 8.5gbps, set_cml[7:0] = 148d, rate_sel = 1, rxde_en = 0 max3945 toc07 20ps/div 100mv p-p k28.5 pattern at 10.3gbps, set_cml[7:0] = 148d, rate_sel = 1, rxde_en = 0 max3945 toc08 18ps/div 100mv p-p k28.5 pattern at 11.3gbps, set_cml[7:0] = 148d, rate_sel = 1, rxde_en = 0 max3945 toc09 18ps/div 100mv p-p
8 ______________________________________________________________________________________ max3945 1.0625gbps to 11.3gbps, sfp+ dual-path limiting amplifier typical operating characteristics (continued) (v cc = 3.3v, t a = +25 n c, unless otherwise noted. registers are set to default values, unless otherwise noted, and the 3-wire interface is static during measurements.) differential output signal level vs. set_cml dac setting max3945 toc10 set_cml dac setting differential output amplitude (mv p-p ) 250 200 100 150 500 600 700 800 1000 900 1100 1200 400 50 300 rxde_en = 0 rxde1 = 0, rxde0 = 0 rxde1 = 0, rxde0 = 1 rxde1 = 1, rxde0 = 0 rxde1 = 1, rxde0 = 1 deemphasis value vs. set_cml dac setting (rate_sel = 1) max3945 toc11 set_cml dac setting deemphasis level (db) 200 150 100 2 4 6 0 50 250 rxde1 = 1, rxde0 = 1 rxde1 = 1, rxde0 = 0 rxde1 = 0, rxde0 = 1 rxde1 = 0, rxde0 = 0 rxde_en = 0 rx input-based los threshold vs. dac code (los1_en = 1 and los2_en = 0) max3945 toc12 set_los[5:0] dac code los threshold (mv p-p ) 60 50 10 20 30 40 20 40 60 80 100 120 140 160 0 0 70 deassert assert rssi monitor-based los thresholds (los1_en = 0 and los2_en = 1) max3945 toc13 set_los[5:0] dac code los threshold (mv) 60 50 30 40 20 10 20 40 60 80 100 120 140 160 180 0 0 70 deassert assert los masking time vs. dac setting max3945 toc14 set_lostimer[6:0] dac code masking time (s) 120 100 80 60 40 20 1000 2000 3000 4000 5000 0 0 deterministic jitter vs. input amplitude at 1.25gbps (k28.5 pattern, 933mhz input filter) max3945 toc15 signal amplitude (mv p-p ) dj (ps) 1000 800 600 400 200 10 15 20 25 5 0 1200 rate_sel = 0, bw1 = 0, bw2 = 0 deterministic jitter at 10.32gbps (prbs7 pattern with 100 cids, rate_sel = 1) max3945 toc16 input signal amplitude (mv p-p ) dj (ps) 1000 800 200 400 600 1 2 3 4 5 6 7 8 9 10 0 0 1200 deterministic jitter vs. data rate (input = 100mv p-p ) max3945 toc17 data rate (gbps) dj (ps) 9 6 3 5 10 15 20 25 0 0 12 k28.5 pattern, rate_sel = 1 dj with 100mv p-p noise on power supply dj with no noise on power supply power-supply current vs. temperature (set_cml[7:0] = 91d) max3945 toc18 temperature (c) power-supply current (ma) 80 60 40 20 0 -20 30 40 50 60 70 80 20 -40 100 los2_en = 0 and los1_en = 1 los2_en = 1 and los1_en = 0
_______________________________________________________________________________________ 9 max3945 1.0625gbps to 11.3gbps, sfp+ dual-path limiting amplifier typical operating characteristics (continued) (v cc = 3.3v, t a = +25 n c, unless otherwise noted. registers are set to default values, unless otherwise noted, and the 3-wire interface is static during measurements.) electrical eye diagram after 6in of fr4 and 72in of cable with deemphasis (11.3gbps k28.5, rate_sel = 1, set_cml[7:0] = 160d, rxde_en = 1, rxde0 = 1, rxde1 = 1) max3945 toc25 20ps/div 80mv/div electrical eye diagram after 6in of fr4 and 72in of cable with no deemphasis (11.3gbps k28.5, rate_sel = 1, set_cml[7:0] = 160d, rxde_en = 0) max3945 toc24 20ps/div 100mv/div transient response (10.3gbps, 10 ones 10 zeros pattern, set_cml[7:0] = 92d) max3945 toc23 time (ps) 800 600 400 200 -0.20 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 0.25 -0.25 0 1000 a c d b a = 1.39db, rxde1 = 0, rxde0 = 0 b = 2.12db, rxde1 = 0, rxde0 = 1 c = 3.27db, rxde1 = 1, rxde0 = 0 d = 4.37db, rxde1 = 1, rxde0 = 1 output common-mode return gain (scc22) (input power of 0dbm, enabled) max3945 toc22 frequency (ghz) scc22 (db) 10 -30 -20 -10 0 -40 1 100 input common-mode return gain (scc11) (input power of 0dbm, enabled) max3945 toc21 frequency (ghz) scc11 (db) 10 -30 -20 -10 0 -40 1 100 output return gain (sdd22) (input power of 0dbm, enabled) max3945 toc20 frequency (ghz) sdd22 (db) 10 1 -30 -20 -10 0 -40 0 100 input return gain (sdd11) (input power of 0dbm, enabled) max3945 toc19 frequency (ghz) sdd11 (db) 10 1 -30 -20 -10 0 -40 0 100
10 _____________________________________________________________________________________ max3945 1.0625gbps to 11.3gbps, sfp+ dual-path limiting amplifier pin configuration pin description 15 16 14 13 5 6 7 v ee los 8 caz sda scl rpmin 1 3 rin- 4 12 10 9 rin+ *ep *the exposed pad must be connected to ground. + v ccr v ccr rout- rout+ v ccr v ee csel 2 11 v ccr thin qfn (3mm 3mm) max3945 top view pin name function 1 caz offset-correction loop capacitor. a capacitor connected between this pin and the adjacent v ee pin sets the time constant of the offset-correction loop. the offset correction can be disabled through the digital interface by setting bit az_en = 0 and by connecting this pin to ground. 2, 3 v ee ground for limiting amplifier 4 los loss-of-signal output. this output is an open-drain output. los is asserted when the level of the input signal drops below the preset threshold set by set_los[5:0]. los is deasserted when the signal level is above the threshold. the polarity of the los output can be inverted by setting los_pol = 0. the los circuitry can be disabled by setting los1_en = 0 and los2_en = 0. see table 8. 5, 8, 13, 16 v ccr power supply. provides supply voltage to the limiting amplifier. all pins must be connected to the supply voltage. 6 rout+ noninverted output, cml. back terminated for 50 i load. 7 rout- inverted output, cml. back terminated for 50 i load. 9 scl serial-clock input, ttl/cmos. this pin has a 75k i internal pulldown. 10 sda serial-data bidirectional i/o. ttl/cmos input and open-drain output. this pin has a 75k i internal pul - lup, but it requires an external 4.7k i pullup resistor to meet the 3-wire digital timing specification. (data line collision protection is implemented.) 11 csel chip-select input, ttl/cmos. internally pulled down by a 75k i resistor. csel = 1 starts an spi cycle, while csel = 0 ends the spi cycle and resets the control state machine. 12 rpmin high-impedance receive power-monitor input. connect to ground when not used. 14 rin- inverted data input, cml, with 50 i termination 15 rin+ noninverted data input, cml, with 50 i termination ep exposed pad. must be soldered to circuit ground.
______________________________________________________________________________________ 11 max3945 1.0625gbps to 11.3gbps, sfp+ dual-path limiting amplifier detailed description the max3945 is designed to operate from 1.0625gbps to 11.3gbps. it consists of a dual-path limiter, offset- correction circuitry, cml output stage, and los circuitry. the characteristics of the max3945 can be controlled through the on-chip 3-wire interface. the registers that control the parts functionality are rxctrl1, rxctrl2, rxstat, set_cml, set_los, modectrl, and set_ lostimer. the max3945 provides integrated dacs to allow the use of low-cost controller ics. figure 1 shows simplified input and output structures. dual-path limiter the limiting amplifier features a low data-rate path (1.0625gbps to 4.25gbps) and a high data-rate path (up to 11.3gbps), allowing for overall system optimiza - tion. figure 2 shows the functional diagram. data path selection is controlled by the rate_sel bit. the low data-rate path further features a programmable filter that provides optimization for 1.0625gbps, 1.25gbps, 2.125gbps, and 4.25gbps operation. it is important to tailor the bandwidth of the first stages to get the best receive sensitivity and to reduce the maximum receive bandwidth for a given data rate. table 1 summarizes the rate_sel, bw1, and bw0 control bit functions. the high data-rate mode (rate_sel = 1) is recommended for operation up to 11.3gbps. the polarity of rout+/rout- relative to rin+/rin- is programmed by the rx_pol bit, as shown in table 2. offset-correction circuitry the offset-correction circuitry is provided to remove pwd caused by intrinsic offset voltages within the dif - ferential amplifier stages. an external 0.1 f f capacitor connected between the caz pin and ground sets the offset-correction loop cutoff frequency to approximately 2khz when rate_sel = 0 and to approximately 0.7khz when rate_sel = 1. the offset-correction loop can be disabled using the az_en bit, as shown in table 3. cml output stage cml output enable and squelch the cml output stage is optimized for differential 100 i loads. the output stage is controlled by a combination of the rx_en and sq_en bits and the internal los status. see table 4. table 1. rate select and bandwidth control table 4. cml output stage operation modes table 2. signal polarity control table 3. offset-correction enable/disable control rxctrl1[3:1] operation mode description bw1 bw0 rate_sel data rate (gbps) filter bandwidth (mhz) rise/fall time (ps) 0 0 0 1.0625 to 1.25 1000 52 0 1 0 2.125 2100 52 1 0 0 2.125 2500 52 1 1 0 4.25 3000 52 x x 1 11.3 9000 26 rx_pol operation mode description 0 inversed polarity of the differential signal path 1 normal polarity of the differential signal path az_en operation mode description 0 autozero loop is disabled 1 autozero loop is enabled rx_en sq_en los status operation mode description 0 x x cml output disabled 1 0 x cml output enabled 1 1 0 cml output enabled 1 1 1 cml output disabled
12 _____________________________________________________________________________________ max3945 1.0625gbps to 11.3gbps, sfp+ dual-path limiting amplifier figure 1. simplified input/output structures 50 ? 50 ? 50 ? 50 ? v ccr v ccr - 1v v ccr v eer v eer rin+ rout+ rout- rin- 75k ? v ccd v eer sda deemphasis control 376 ? v eet los rpmin 75k ? v ccd v eer scl, csel v ccr comparator 2pf clamp 2k? 2k? dac
______________________________________________________________________________________ 13 max3945 1.0625gbps to 11.3gbps, sfp+ dual-path limiting amplifier cml output deemphasis the cml output stage is optimized for differential 100 i transmission lines on a standard fr4 board. the rxde1 and rxde0 bits add programmable analog output deemphasis to compensate for fr4 board losses and sfp connector losses. table 5 describes the deempha - sis control settings. programmable cml output amplitude the 8-bit set_cml register controls the amplitude of the cml output stage. the maximum programmable output level depends on the operational mode of the max3945. these output levels (which assume an ideal 100 i dif - ferential load) and their corresponding control bits are described in table 6. table 7 shows the output dac resolution dependency. figure 2. functional diagram rin+ sda scl csel v ccr rpmin v ccr - 1v bw1 r in r pull r pull r in rin- bw0 rate_sel rx_pol az_en 4g 10g 1 0 mx lpf digital offset correction deemphasis rxde1 rout+ caz rout- los rxde0 rx_en sq_en v ccr r out r out output ctrl logic loss of signal los_pol los2/1_en r pull v ee 3-wire interface internal register control logic 7b dac set_lostimer 8b dac set_cml 6b dac set_los v ccr max3945 1 0
14 _____________________________________________________________________________________ max3945 1.0625gbps to 11.3gbps, sfp+ dual-path limiting amplifier table 5. output signal deemphasis control table 6. cml output amplitude range (typical) table 7. cml output dac resolution (typical) rxctrl2[1] rxctrl1[7:6] operation mode description rxde_en rxde1 rxde0 mode deemphasis (db) 0 x x deemphasis block is disabled 0 1 0 0 deemphasis block is enabled level 1 0.3 1 0 1 deemphasis block is enabled level 2 1.1 1 1 0 deemphasis block is enabled level 3 2.1 1 1 1 deemphasis block is enabled level 4 4.3 rxctrl1[1] rxctrl2[1] rxctrl1[7:6] mode output amplitude (mv p-p ) rate_sel rxde_en rxde1 rxde0 0 x x x low data-rate path 400 to 1192 1 0 x x high data-rate path 400 to 1147 1 1 0 0 high data-rate path with deemphasis 400 to 1041 1 1 0 1 high data-rate path with deemphasis 400 to 987 1 1 1 0 high data-rate path with deemphasis 400 to 908 1 1 1 1 high data-rate path with deemphasis 400 to 828 rxctrl1[1] rxctrl2[1] rxctrl1[7:6] mode resolution (mv p-p ) rate_sel rxde_en rxde1 rxde0 0 x x x low data-rate path 4.5 1 0 x x high data-rate path 4.5 1 1 0 0 high data-rate path with deemphasis 4.1 1 1 0 1 high data-rate path with deemphasis 3.9 1 1 1 0 high data-rate path with deemphasis 3.6 1 1 1 1 high data-rate path with deemphasis 3.3
______________________________________________________________________________________ 15 max3945 1.0625gbps to 11.3gbps, sfp+ dual-path limiting amplifier los circuitry the los circuitry has two operational modes controlled by the los1_en and los2_en bits (see table 8). in the first mode, the los block detects the differential ampli - tude of the input signal and compares it against a preset threshold controlled by the 6-bit set_los register. in the second mode, the los block compares the voltage at the rpmin pin to a preset threshold also controlled by the 6-bit set_los register. the second mode enables low-power los detection based on average photodiode current. the los assert threshold is approximately 1.5mv p-p x set_los[5:0]. the los deassert level is approximately 1.6 times the assert level to avoid los chatter. los polarity, squelch, and los masking time are unaffected by the selection of los1_en or los2_en. programmable los output masking time this feature masks false input signals that can occur after a loss-of-light event in a fiber optic link. these false input signals, caused by some transimpedance amplifier implementations, can corrupt the los output and cause system-level link diagnostic errors. the los output masking time can be programmed from 0 to 4500 f s in 35 f s steps using the 7-bit set_lostimer[6:0] register. the output mask timer is initiated on the first transition of the los signal and prevents any further changes in the los output signal until the end of the programmed los timing period. the los output mask - ing time should be carefully chosen to extend beyond any expected input glitch. figure 3 shows the los signal changing after approximately 800 f s to a change in the input signal where the los output masking time function is not used. figure 4 shows masking of the los signal by the los output masking time function to a change in the input signal. table 8. los control figure 3. los response to a short burst of input signal figure 4. los response to a short burst of input signal (any changes in los are masked until the end of the los masking period.) 400s/div 50mv/div 2mv/div 400s/div 50mv/div 2mv/div los2_en los1_en operation mode description 0 0 los circuitry is disabled and powered down x 1 los circuitry is enabled and rx input amplitude is detected 1 0 los circuitry is enabled and rpmin input amplitude is detected
16 _____________________________________________________________________________________ max3945 1.0625gbps to 11.3gbps, sfp+ dual-path limiting amplifier 3-wire digital communication general the max3945 implements a proprietary 3-wire digital interface. an external controller generates the clock. the 3-wire interface consists of an sda bidirectional data line, an scl clock signal input, and a csel chip-select input (active high). the external master initiates a data transfer by asserting the csel pin. the master starts to generate a clock signal after the csel has been set to 1. all data transfers are most significant bit (msb) first. protocol each operation consists of 16-bit transfers (15-bit address/data, 1-bit rwn). the bus master generates 16 clock cycles to scl. all operations transfer 8 bits to the max3945. the rwn bit determines if the cycle is read or write. see table 9. register addresses the max3945 contains seven registers available for pro - gramming. table 10 shows the registers and addresses. write mode (rwn = 0) the master generates 16 total clock cycles at scl. the master outputs a total of 16 bits (msb first) to the sda line at falling edge of the clock. the master closes the transmission by setting csel to 0. figure 5 shows the interface timing, and table 11 defines the various timing parameters. read mode (rwn = 1) the master generates 16 total clock cycles at scl. the master outputs a total of 8 bits (msb first) to the sda line at falling edge of the clock. the sda line is released after the rwn bit has been transmitted. the slave outputs 8 bits of data (msb first) at rising edge of the clock. the master closes the transmission by setting csel to 0. figure 5 shows the interface timing. mode control normal mode allows read-only instruction for all registers except modectrl. normal mode is the default mode. setup mode allows the master to write unrestricted data into any register except the rxstat register. to enter setup mode, the modectrl register (address = h0x0e) must be set to h0x12. after the modectrl register has been set to h0x12, the next operation is unrestricted. the setup mode is automatically exited after the next operation is finished. this sequence must be repeated if further unrestricted settings are necessary. table 9. digital communication word structure table 10. register descriptions and addresses bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 register address rwn data that is written or read. address name function h0x00 rxctrl1 receiver control register 1 h0x01 rxctrl2 receiver control register 2 h0x02 rxstat receiver status register h0x03 set_cml cml output level setting register h0x04 set_los los threshold assert level setting register h0x0e modectrl general control register h0x12 set_lostimer los timer setting register
______________________________________________________________________________________ 17 max3945 1.0625gbps to 11.3gbps, sfp+ dual-path limiting amplifier register descriptions receiver control register 1 (rxctrl1) bits 7 and 6: rxde[1:0]. these 2 bits are used to control deemphasis of the output waveform. see table 5 for the bit settings and corresponding deemphasis levels. bit 4: softres. when this bit is set to 1 during a 3-wire interface write operation, all registers are set to the default state when csel goes low. bits 3 and 2: bw[1:0]. when rate_sel = 0, these 2 bits control the bandwidth of the limiting amplifier. see table 1 for the settings and corresponding filter selection. bit 1: rate_sel. rate_sel selects between the low bandwidth data path (1.0625gbps to 4.25gbps) and the high bandwidth data path (4.25gbps to 11.3gbps). when rate_sel is set to 1, the high bandwidth path is chosen. when rate_sel is set to 0, the low bandwidth path is chosen. figure 5. timing for the 3-wire digital interface table 11. interface timing parameters * do not change default setting. csel scl sda csel scl sda 1 2 3 4 5 6 7 8 a6 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 a5 a4 a3 a2 a1 rwn d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 rwn write mode read mode a0 a6 a5 a4 a3 a2 a1 a0 t l t l t ch t cl t ds t dh t ch t cl t ds t d t dh t t t t symbol definition t l csel leading time before the first scl edge t ch scl pulse-width high t cl scl pulse-width low t d scl rise to sda propagation time t ds sda setup time t dh sda hold time t t csel trailing time after last scl edge bit # 7 6 5 4 3 2 1 0 address name rxde1 rxde0 x* softres bw1 bw0 rate_sel x* h0x00 default value 0 0 1 0 1 1 1 1
18 _____________________________________________________________________________________ max3945 1.0625gbps to 11.3gbps, sfp+ dual-path limiting amplifier receiver control register 2 (rxctrl2) bit 7: los2_en. enables or disables the rssi monitor-based los circuitry, in combination with the los1_en bit. the below table shows when the rssi monitor-based los is disabled and enabled. bit 6: los1_en. controls the rx input-based los circuitry. when rx_en is set to 0, the los detector is also disabled. 0 = disabled 1 = enabled bit 5: los_pol. controls the polarity of the los pin. 0 = inverse 1 = normal bit 4: rx_pol. controls the polarity of the cml output. 0 = inverse 1 = normal bit 3: sq_en. when sq_en = 1, the cml output is squelched when los is asserted. 0 = disabled 1 = enabled bit 2: rx_en. enables or disables the receive circuitry. 0 = disabled 1 = enabled bit 1: rxde_en. enables or disables the deemphasis on the cml output. 0 = disabled 1 = enabled bit 0: az_en. enables or disables the autozero circuitry. 0 = disabled 1 = enabled bit # 7 6 5 4 3 2 1 0 address name los2_en los1_en los_pol rx_pol sq_en rx_en rxde_en az_en h0x01 default value 0 1 1 1 0 1 0 1 los2_en los1_en rx_en rx input-based los rssi monitor-based los 0 0 x disabled and powered down disabled and powered down 0 1 1 enabled disabled and powered down x 1 0 disabled and powered down disabled and powered down 1 1 1 enabled disabled and powered down 1 0 0 disabled and powered down enabled 1 0 1 disabled and powered down enabled
______________________________________________________________________________________ 19 max3945 1.0625gbps to 11.3gbps, sfp+ dual-path limiting amplifier receiver status register (rxstat) bit 1: por_2d. when the v cc supply voltage is below 2.3v, the por circuitry sets por_2d high. when the supply voltage is above 2.75v, the por circuitry deasserts, but the por_2d bit remains high until it is read. bit 0: los_2d. copy of the los status. this is a sticky bit, which means that it is cleared on a read. the first 0-to-1 transition is latched until the bit is read by the master or por occurs. cml output level setting register (set_cml) bits 7 to 0: set_cml[7:0]. the set_cml register is an 8-bit register that can be set up to 255 for maximum cml output amplitude. see table 13 for equations to determine cml output level vs. set_cml. los threshold assert level setting register (set_los) bits 5 to 0: set_los[5:0]. the set_los register is a 6-bit register used to program the los threshold. see the typical operating characteristics section for a typical los threshold voltage vs. dac code for both the rx input-based los and the rssi monitor-based los. bit # 7 6 5 4 3 2 1 (sticky) 0 (sticky) address name x x x x x x por_2d los_2d h0x02 default value x x x x x x x x bit # 7 6 5 4 3 2 1 0 address name set_cml[7] (msb) set_cml[6] set_cml[5] set_cml[4] set_cml[3] set_cml[2] set_cml[1] set_cml[0] (lsb) h0x03 default value 0 1 0 1 1 1 0 0 bit # 7 6 5 4 3 2 1 0 address name x x set_los[5] (msb) set_los[4] set_los[3] set_los[2] set_los[1] set_los[0] (lsb) h0x04 default value x x 0 0 1 1 0 0
20 _____________________________________________________________________________________ max3945 1.0625gbps to 11.3gbps, sfp+ dual-path limiting amplifier general control register (modectrl) bits 7 to 0: modectrl[7:0]. the modectrl register enables a switch between normal and setup modes. the setup mode is achieved by setting this register to h0x12. modectrl must be updated before each write operation. los timer setting register (set_lostimer) bits 6 to 0: set_lostimer[6:0]. the set_lostimer register is a 7-bit register that can be set from 0 to 127. see the typical operating characteristics section for a typical timer period vs. dac code. table 12. register map bit # 7 6 5 4 3 2 1 0 address name modectrl[7] (msb) modectrl[6] modectrl[5] modectrl[4] modectrl[3] modectrl[2] modectrl[1] modectrl[0] (lsb) h0x0e default value 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 address name x set_ lostimer[6] (msb) set_ lostimer[5] set_ lostimer[4] set_ lostimer[3] set_ lostimer[2] set_ lostimer[1] set_ lostimer[0] (lsb) h0x12 default value x 0 0 0 0 0 0 0 register function/ address register name normal mode setup mode bit number/ type bit name default value notes receiver control register 1 address = h0x00 rxctrl1 r rw 7 rxde1 0 rx deemphasis msb control with rxde_en = 1 r rw 6 rxde0 0 rx deemphasis lsb control with rxde_en = 1 r rw 5 x 1 must be set to 1 r rw 4 softres 0 soft reset control bit r rw 3 bw1 1 input bandwidth control with rate_sel = 0: 00: 1ghz 01: 2.1ghz 10: 2.5ghz 11: 3ghz r rw 2 bw0 1 r rw 1 rate_sel 1 rate-select con - trol 0: 1g/4g mode 1: fast mode r rw 0 x 1 must be set to 1
______________________________________________________________________________________ 21 max3945 1.0625gbps to 11.3gbps, sfp+ dual-path limiting amplifier table 12. register map (continued) register function/ address register name normal mode setup mode bit number/ type bit name default value notes receiver control register 2 address = h0x01 rxctrl2 r rw 7 los2_en 0 rssi monitor- based los 0: disabled 1: enabled when los1_en = 0 r rw 6 los1_en 1 rx input-based los 0: disabled 1: enabled r rw 5 los_pol 1 los polarity 0: inverse 1: normal r rw 4 rx_pol 1 rx polarity 0: inverse 1: normal r rw 3 sq_en 0 squelch 0: disabled 1: enabled r rw 2 rx_en 1 rx control 0: disabled 1: enabled r rw 1 rxde_en 0 rx deemphasis 0: disabled 1: enabled r rw 0 az_en 1 rx autozero control 0: disabled 1: enabled receiver status register address = h0x02 rxstat r r 1 (sticky) por_2d x por -> v cc low limit violation r r 0 (sticky) los_2d x copy of los status
22 _____________________________________________________________________________________ max3945 1.0625gbps to 11.3gbps, sfp+ dual-path limiting amplifier table 12. register map (continued) register function/ address register name normal mode setup mode bit number/ type bit name default value notes cml output level setting register address = h0x03 set_cml r rw 7 set_cml[7] 0 msb output level dac r rw 6 set_cml[6] 1 r rw 5 set_cml[5] 0 r rw 4 set_cml[4] 1 r rw 3 set_cml[3] 1 r rw 2 set_cml[2] 1 r rw 1 set_cml[1] 0 r rw 0 set_cml[0] 0 lsb output level dac los threshold assert level setting register address = h0x04 set_los r rw 5 set_los[5] 0 msb los thresh - old dac r rw 4 set_los[4] 0 r rw 3 set_los[3] 1 r rw 2 set_los[2] 1 r rw 1 set_los[1] 0 r rw 0 set_los[0] 0 lsb los thresh - old dac general control register address = h0x0e modectrl rw rw 7 modectrl[7] 0 msb mode con - trol rw rw 6 modectrl[6] 0 rw rw 5 modectrl[5] 0 rw rw 4 modectrl[4] 0 rw rw 3 modectrl[3] 0 rw rw 2 modectrl[2] 0 rw rw 1 modectrl[1] 0 rw rw 0 modectrl[0] 0 lsb mode con - trol los timer setting register address = h0x12 set_lostimer r rw 6 set_lostimer[6] 0 msb los timer r rw 5 set_lostimer[5] 0 r rw 4 set_lostimer[4] 0 r rw 3 set_lostimer[3] 0 r rw 2 set_lostimer[2] 0 r rw 1 set_lostimer[1] 0 r rw 0 set_lostimer[0] 0 lsb los timer
______________________________________________________________________________________ 23 max3945 1.0625gbps to 11.3gbps, sfp+ dual-path limiting amplifier design procedure programming cml output levels see tables 13 and 14. for each value of the bits rxde1 and rxde0 in table 13, the value of deempha - sis does vary with the set_cml[7:0] setting. in table 13, the values of deemphasis are given for the setting set_cml[7:0] = 120d. the variation of deemphasis for other values of set_cml[7:0] is shown in the typical operating characteristics (see the deemphasis value vs. set_cml dac setting (rate_sel = 1) graph). note that even though rxde_en = 0, there is still some deem - phasis for rate_sel = 1 for values of amplitude control below set_cml[7:0] = 170d. select the coupling capacitor for ac-coupling, the coupling capacitors c in and c out should be selected to minimize the receivers determin - istic jitter. jitter is decreased as the input low frequency cutoff (f in ) is decreased: f in = 1/[2 g (50)(c in )]. the recommended value of c in and c out is 0.1 f f for the max3945. select the offset-correction capacitor the capacitor between caz and ground determines the time constant of the signal path dc-offset cancellation loop. a 0.1 f f capacitor between caz and ground is recommended for the max3945. applications information layout considerations use good, high-frequency layout techniques and mul - tiple-layer boards with uninterrupted ground planes to minimize emi and crosstalk. exposed-pad package the exposed pad on the 16-pin tqfn provides a very low-thermal resistance path for heat removal from the ic. the pad is also electrical ground on the max3945 and must be soldered to the circuit board ground for proper thermal and electrical performance. refer to application note 862: hfan-08.1: thermal considerations of qfn and other exposed-paddle packages for additional information. table 13. cml output amplitude equations (typical) table 14. set_cml dac codes for 400mv p-p and 800mv p-p output levels rxctrl1[1] rxctrl2[1] rxctrl1[7:6] deemphasis (db) (set_cml[7:0] = 120d) equation for (v rout+ - v rout- ) rate_sel rxde_en rxde1 rxde0 0 x x x 0 45mv p-p + 4.5mv p-p x set_cml 1 0 x x 0.72 4.5mv p-p x set_cml 1 1 0 0 1.17 -4mv p-p + 4.1mv p-p x set_cml 1 1 0 1 1.89 -7mv p-p + 3.9mv p-p x set_cml 1 1 1 0 2.48 -10mv p-p + 3.6mv p-p x set_cml 1 1 1 1 3.86 -13mv p-p + 3.3mv p-p x set_cml rxctrl1[1] rxctrl2[1] rxctrl1[7:6] set_cml dac code rate_sel rxde_en rxde1 rxde0 400mv p-p 800mv p-p 0 x x x 80 169 1 0 x x 91 181 1 1 0 0 98 194 1 1 0 1 106 208 1 1 1 0 115 225 1 1 1 1 126 245
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 24 maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. max3945 1.0625gbps to 11.3gbps, sfp+ dual-path limiting amplifier package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. typical application circuit max3945 los rout+ rout- v ee ep caz 0.1f c out 0.1f 0.1f c in 0.1f rin+ rpmin v ccr rin- scl csel sda 0.1f 4.7k ? r rpmin 2k? i rpmin 100pf 10g pin flex rosa 3-wire interface 11.3gbps power-on reset +3.3v sfp+ optical receiver sfp connector host board vcc_rx +3.3v 3-wire interface adc i 2 c sfp+ controller mode_def2 (sda) mode_def1 (scl) rate select supply filter host filter z diff = 100 ? serdes package type package code document no. 16 tqfn-ep t1633+5 21-0136

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